Layout Proposal (obsolete):

Key Features

  • 4 times LFE3-70E(A)-8FN672C for TDC (+ future applications, as e.g. ADC-readout )
  • 1 central LFE3-150EA-8FN1156C

all at highest speed grade to reduce the development time. ECP3 70/95/150 are supposed to be mostly pin-compatible, so FPGA can be exchanged later if necessary. (Confirmation of Lattice arrived.)

  • smaller 48V power supply, based on Vicors BCM:, B048F060T24 is the type
  • all other PoL regulators based on the Enpirion Products (evaluation board and devices are here at GSI): or similar
  • Add pads / holes around DCDC converters to replace them with an addon board (to use linear regulators in case the DCDC converters produce too much noise in analog data)
  • 2 times 2 SFPs to the central FPGA: 2 for Ethernet and 2 for TRBNet (for example). The position is not really fixed as shown in the layout-proposal. Can be spread over the board.


For the TDC functionality a direct clock with fanout will give a better performance. Here TI is very good, as we know: The TDC needs a 200MHz clock (SiS.type as on all other boards). -> 100 MHz system clock can easily be generated from this clock. Thus use two onboard clock networks: 125 MHz and 200 MHz. Proposed layout: 2 CLK5410 chips, both inputs on both chips equipped with oscillators (one input used, one free). From one CLK5410 chip put one line to one Serdes of each FPGA and one line to a PCLK input (2,3,6,7). From the other CLK5410 chip put one line to one Serdes of each FPGA and one line to a GPLL input on the left/right side of each FPGA. But we need the direct clock (200MHz after fanout) to a clock input of each FPGA for the TDC. New requirement (R3B): The board has to be able to run on an external clock. So, one differential line from the RJ45 connector schoul go to one of the clock managers. This will do what we need.


  • we leave the add-on connectors as they are on v2 controlled by the central FPGA.

  • The connectors to each FPGA should be Samtec: QMS-104-09.75-L-D-A (mating part: QFS-104-06.25-L-D-A): Length 8,5cm These high speed connectors are similar to the AddOn connectors of the TRBv2, but are more rugged. They provide 208 pins + 3 power blades. Used by Jan Hoffmann and recommended by him.

The idea is to use the lower 80 pins exactly as used on the TRBv2 to be able to use the TRBv2 in the existing setups. (A small adapter board to the KEL-connectors has to be built for that). On the other hand, these connectors allow to build small AddOns which have the additional possibility to connect to 128 more pins (+ power). This allows to read out with the FPGA (LFE3-70) on the TRB for example ADCs or other devices. Then we have the TDC and ADC data all available in one FPGA and in total a board with 128 channels. Application: ECal for example.

The pinout of the remaining 128 pins has to be chosen carefully (to be done). Please help!

  • Standard reference time input: This then is fed to a fan-out chip, which will be fed to the FPGAs (twice as Marek said). And a RJ45 as secondary reference time input. (The input of the fanout-chips can select between two inputs. This can be done via a jumper.)

  • Additional auxilary connectors, like RJ45 + a normal pitch pin-header, all connected to the central FPGA. *Many LEDs! (Please label them LED1..8, not dgood, dwait etc.) maybe 4 for each FPGA. And a test connector for each of the 4 FPGAs.

Connection between FPGA:

  • SERDES connections
  • Each of the TDC-FPGAs has two SERDES connections to the central FPGA, coming from two QUADS. If possible, put one line of one quad to the mini-addon-connector. Put a set of 12 LVCMOS25 lines between the central FPGA and each of the other FPGAs
All 4 FPGAs have identical schematics and layout!

  • Each FPGA gets a FLASH to boot from.
From the MDC-Hub2 we learned: Connect the programming lines from all flashs to the central FPGA - this way a broken Flash can be restored since the central FPGA is not affected by an upgrade of the other four FPGA. (There is no nice way to recover the central FPGA, but this one will be upgraded much more seldomly). (see comments)

  • JTAG chain.

  • DDR2-3 RAM and SRAM I would skip on the 4 FPGAs, I don't see the obvious application.
  • Maybe an SRAM on the central FPGA. DDR3 is tricky and not !

After reading TN1180 I would rather avoid DDR unless we really need it. If we need it we have to write vhdl code with proper constraints and without any drc errors before pin assignment. (Which is the usual way how to design boards in general...)

  • Two bit coding input to select the FPGA number - like on the MDC Hub2


  • Marcin: schematics: started on 2011-02-07
  • Pinout definition: all, please help
  • Greg can start with the UDP-communication protocol, replacing the ETRAX by a PC: start 2011-02-14
  • Layout and production: Peter and Michael
  • TRBNet implementation: Jan
  • TDC-implementation: Cahit + Eugen
  • TDC-Data-analyis, feature check etc.: Marek

-- JanMichel - 07 May 2012
Topic revision: r1 - 07 May 2012, JanMichel
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