TigerSHARC

PIN Number of CMOS-PINs Comments PINs connected to Virtex4
SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0
SCLK 1 to lattice clock driver, 125MHz, if less, change SCLKRAT 0
RST_IN 1 Virtex should reset the DSP 1
RST_OUT 1 conn. to POR_IN  
    conn. in addition to Vitrex 1
POR_IN 1 conn. to RST_OUT 0
ADDR 32 conn. to Virtex 32
DATA0-31 32 conn. to Virtex 32
DATA32-63 32 NC 0
RD, WRL, WRH 3 conn. to VIRTEX in any case 3
ACK 1 conn. to VIRTEX in any case 1
BMS 1 Output after reset, but input during reset, selects boot via LP/Host, very important!!! 1
    otherwise the DSP tries to boot via EEPROM  
MS 2 unconnected, no external memory 0
MSH 1 conn to Virtex, access to host maybe usefull? 0
BRST 1 to VIRTEX 1
BR0 1 output, since DSP000, -> NC 0
BR1-7 7 pulled up to VDD_IO via Resistor 0
ID0-2 3 unconnected, has internal pull down 0
BM 1 NC 0
BOFF 1 to VIRTEX 1
BUSLOCK 1 to VIRTEX 1
HBR, HBG 2 to VIRTEX, important! 2
CPA 1 not needed, leave unconnected 0
DPA 1 not needed, leave unconnected 0
DMAR0-3 4 to VIRTEX 4
IOWR, IORD, IOEN 3 to VIRTEX 3
MSSD0-3 4 not needed, leave unconnected 0
RAS, CAS, LDQM 3 not needed, leave unconnected 0
SDA10, SDCKE, SDWE 3 not needed, leave unconnected 0
EMU 1 JTAG needed? 0
TCK 1 JTAG 0
TDI 1 JTAG 0
TDO 1 JTAG 0
TMS 1 JTAG – important to pull down during powerup !!! (famous TIP bug) 0
TRST 1 JTAG 0
FLAG0-3 4 to VIRTEX 4
IRQ0-3 4 to VIRTEX 4
TMROE 1 Output: Timer, most likely not needed 1
    During Reset: Input, must be HIGH at Reset (otherwise LP one 1bit  
LxACKI 4 Link Port 4
LxBCMPO 4 Link Port for DMA 4
LxACKO 4 LP 4
LxBCMPI 4 LP 4
CONTROLIMP0,1 2 Needs Pull-down 0
DS0-2 3 should match board imepdance -> Question to board layouter, Imp goes from 26Ohm->120Ohm 0
ENEDREG 1 connect to VSS 0
Total to XILINX     108

PIN Number of LVDS-PAIRs Comments PINs connected to Virtex4
LxDATO0-3 12   24
LxCLKOUT 4   8
LxDATI0-3 12 if not conn -> pull up to VDD_IO 24
LxCLKIN0-3 4 if not conn -> pull up to VDD_IO 8
Total to XILINX     64

Unclear: How many link-ports do we need? At least 2, maybe all 4?

Power Pins:

  • VDD 1.05V for 500MHz, 1.20V for 600MHz
  • VDD_A (for the PLL, very important to make a good decoupling!!!) same value as VDD
  • VDD_IO 2.5V
  • VDD_DRAM 1.5V for 500MHz, 1.6V for 600MHz

filter

ALERT! There is a nice app note from XILIX: (XAPP727) with PCB design rules for connecting the TS20x LP to a Virtex4: http://direct.xilinx.com/bvdocs/appnotes/xapp727.pdf This link is not easily available, therefore I uploaded the xapp727 in our wiki. (Michael)
Topic attachments
I Attachment Action Size Date Who Comment
xapp727.zipzip xapp727.zip manage 818.9 K 23 Jun 2006 - 19:27 MichaelTraxler Application note from Xilinx
Topic revision: r2 - 27 Oct 2009, JanMichel
 
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