Errors found in the MDC-Optical-AddOn1 design

  1. The silk-screen (text on the PCB) of the LEDs are not corresponding to the FOT number. So, e.g. FOT13 has a LED with the text RX5 or so.
  2. The connections between the two FPGAs are not ideal, as some of the buses are crossing banks, which makes big problems with the timing of parallel buses. As the split has to be done it could at least be the same at both FPGAs.
  3. The temperature sensor should be connected also to the FPGA, not only to the Etrax. (workaround: Connect JT32 to via of R174 (side facing to fpga1) - not perfect due to 2.5V port-IO voltage, but seems to work)
  4. C9 is switched in polarity.
  5. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  6. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
  7. The Pins of the 48V DCDC converter are quite long - risk of shorts when connected to a TRB even with distance pieces.
  8. FPGA3 has no dedicated reset signal from Power Manager
  9. FPGA1 has no dedicated reset signal from Power Manager
  10. FPGA2 / Serdes LLC0 (TX/RX1): RX and TX are mixed up!
  11. SFP are missing pull-resistors
  12. VCCAUX33 for FPGA3 is wrongly connected to 1.2V, but should be connected to 3.3V. Patch: Tilt up L18 (right side up, left side soldered to the "plane for FPGA") and connect a wire from this open pin to L14 (right side, 3,3V).

Errors found in the Hub2-AddOn design

  • Equip CMLOSC03 with 531KA100 - 100 MHz CML oscillator
  • Equip CMLOSC02 with 531KA125 - 125 MHz CML oscillator
  • Temperature Sensor patch: Connect Temperature Sensor to FPGA1: FPGA-pin H1(lower left pin with testpad) to Pin 80 of AddOn-Connector JTRB2. (see TrbPatches)
  • Disconnect ADO_TTL_46 from AddOn-Connector. This pin is now used as Onewire-Transport between both fpga

Errors found in the Shower AddOn2 design

  • SDIO port of ADC is connected to LVTTL bank - should be LVCMOS25 or lower due to 1.79V U_h_out of ADC
  • D* LED are connected to wrong supply voltage (3.3V, but connected to 2.5V bank)
  • H_FEB_ODD, H_FEB_ENABLE and H_FEB_EVEN are switched in polarity
Topic revision: r6 - 10 Feb 2010, JanMichel
 
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