LVL1 Trigger

Definitions

  • All information about LVL1 triggers will be sent in a packet using TrbNet and the optical network.

  • A fast trigger strobe for an exact timing is delivered on an extra cable.

  • Each trigger strobe must be followed by an trigger information packet on the network before a new trigger strobe is sent. This is controlled by the CTS.

  • The trigger release is to be sent as soon as possible, already when you know that you will be able to accept another trigger in a few microseconds.

Tasks for each endpoint

  • When receiving a trigger acquire all data from the detector and store them in an internal memory until a query is received on the IPU / LVL2 channel.

  • Count the incoming trigger strobes and compare this counter to the received trigger number. If there is a mismatch, set the appropriate bit in the error pattern and release the trigger. All necessary actions to resynchronize will be done by the CTS via DetectorControlSystem.

  • Watch the common control registers and reset your internal trigger strobe counter if the corresponding bit is set.

Data included in the LVL1 trigger packet

The trigger data packet has space for 36 Bit of trigger information

  • a 16 bit counter

  • 8 bit random data (to minimize risk of event mixing)

  • 4 bit trigger code

  • 24 bits for additional information (will be defined soon, Jan, 03.11.09)

Positions in the network packet are as follows:
Bits Content
63 - 40 Additional Information
39 - 32 Random Data
31 - 16 16 bit counter
3 - 0 Trigger Type

Sending test-triggers via Etrax-FPGA-Interface

A LVL1 "trigger" is sent by the following simple procedure:

  • write the error pattern to the corresponding 32bit register (see bit definitions below)

  • write trigger type to the start register (and don't forget the short transfer bit!)

  • done

An example: you want to sent trigger type 0xe, trigger number 0x1234, trigger random 0xab and trigger information 0xcd. So you have to write the error register (offset 0x112) with 0xcdab1234 first. Next write to start register with 0x0000010e will start the trigger transmission. Accessing the FIFO is not necessary.

Bit definition for error register:
Bits Content
31 - 24 Additional Information
23 - 16 Random Data
15 - 0 16 bit counter

Trigger receiver interface

The entity trb_net16_trigger provides an interface receive triggers and to release the trigger after processing has been finished.

Name Width Description
TRG_TYPE_OUT 4 the old trigger code
TRG_NUMBER_OUT 16 trigger number
TRG_RANDOM_CODE_OUT 8 a random code to prevent "trigger number guessing"
TRG_INFORMATION_OUT 24 spare bits for any kind of information
TRG_RECEIVED_OUT 1 rising edge signals received trigger and valid trigger data, falling edge comes one cycle after trg_release is high
TRG_RELEASE_IN 1 the busy release signal, should be set 'as soon as possible'
TRG_ERROR_PATTERN_IN 32 the standard error pattern

-- JanMichel - 19 Dec 2008
Topic revision: r9 - 27 Nov 2018, PeterZumbruch
 
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