SPI controller description

The SPI FlashROM controller is attached to RegIO data bus. The user interface consists of two 32bit registers, and one BlockRAM for data handling.

Any data read from SPI will be written to the BlockRAM, any data to be written to SPI must be setup in the BlockRAM before starting the SPI hardware access.

The SPI FlashROM (AT26DF321) is internally divided into sectors, blocks and pages. Sectors are 64kB sized and are used for protecting/unprotecting different areas. Blocks are 64kB, 32kB or 4kB sized and are used for BlockErase commands. Pages are 256B sized and are used for PageProgram command.

CTRL register

Offset 0xd000, read/write

D[31:24]	CMD	command byte for SPI access
D[23:16]	ADH	address high byte for certain SPI commands
D[15:8]	ADM	address mid byte for certain SPI commands
D[7:0]	ADL	address low byte for certain SPI commands

This register can be read anytime the SPI controller is not busy. In case of an ongoing SPI access this register will answer on TRBnet level with NO_MORE_DATA flag set in the common status bits of the TERM.

This applies only to the time while the SPI controller is busy with the SPI bus operation - for example, after a PageProgram the SPI controller will be busy about 110us, then it is ready again. But the SPI FlashROM will be busy for several milliseconds, as it performs the actual flash process. This can only be found out by reading the status register.

Writing this register will actually start the SPI hardware access. Before writing this register make sure that the MAX value in the SETUP register has been set correctly!

SETUP register

Offset 0xd001, read/write

D[31:24]	MAX	((number of byte to read/write as data) - 1)
D[23:0]	res.	reserved, write with 0x000000

The MAX value sets the number of bytes to be read/written on SPI bus. Please note that at if data is read/written with a SPI command, at least one byte will be transfered, so the register value denotes the (number of bytes - 1). A maximum number of 256bytes can be handled with one SPI command (MAX = 0xff), a minimum of 1byte will be handled by MAX = 0x00.

The SPI controller allows sending any arbitrary number of bytes between 1 and 256. There is no need to watch out of 16bit oder 32bit aligments!

BlockRAM

Offset 0xd100, size 64 32bit words, read/write

Please mind: the contents of this BlockRAM will be overwritten by the SPI controller any time you read data from SPI devices. It is used for all data transports with all SPI commands, including ReadStatusRegister.

Memory organisation:

0xd100:	D[31:24]	D[23:16]	D[15:8]	D[7:0]
	byte3	byte2	byte1	byte0
0xd101:	D[31:24]	D[23:16]	D[15:8]	D[7:0]
	byte7	byte6	byte5	byte4
0xd102:	D[31:24]	D[23:16]	D[15:8]	D[7:0]
	byte11	byte10	byte9	byte8

byte0 is the first byte read/written, byte1 the next, and so on.

Supported SPI commands

Command byte only

• WriteEnable: CMD = 0x06
  • sets the WriteEnableLatch bit in the StatusRegister to '1'
  • must be send before any command altering FlashROM contents

• WriteDisable: CMD = 0x04
  • sets the WriteEnableLatch bit in the StatusRegister to '0'

• ChipErase: CMD = 0xc7
  • erases the whole FlashROM.
  • DO NOT USE DUE TO SILICON BUGS INSIDE THE AT26DF321!
  • USE SectorEraseXX instead

• DeepPowerDown: CMD = 0xb9
  • DO NOT USE

• ResumePowerDown: CMD = 0xab
  • DO NOT USE

Command byte + data readback

• ReadManId: CMD = 0x9f, MAX = 0x03
  • reads the manufactorer ID, device ID and additional information
  • can be used to identify the SPI FlashROM

• ReadStatusRegister: CMD = 0x05, MAX = 0x00...0xff
  • reads one byte information from status register
  • must be used for BUSY polling and programming status

Command byte + 1 byte write

• WriteStatusRegister: CMD = 0x01, MAX = 0x00, one data byte
  • can be used for GlobalProtect/UnProtect
  • WriteEnable command must be issued first
  • DO NOT USE

Command byte + 3 address bytes

• BlockErase64: CMD = 0xd8, ADH:ADM:ADL
  • erases one 64kB block, given by any address inside the sector
  • sector must be unprotected first
  • WriteEnable command must be issued first

• BlockErase32: CMD = 0x52, ADH:ADM:ADL
  • erases one 32kB block, given by any address inside the sector
  • sector must be unprotected first
  • WriteEnable command must be issued first

• BlockErase4: CMD = 0x20, ADH:ADM:ADL
  • erases one 4kB block, given by any address inside the sector
  • sector must be unprotected first
  • WriteEnable command must be issued first

• SectorProtect: CMD = 0x36, ADH:ADM:ADL
  • WriteEnable command must be issued first
  • protects one sector from being altered

• SectorUnprotect: CMD = 0x39, ADH:ADM:ADL
  • WriteEnable command must be issued first
  • unprotects one sector and allows changing its contents

Command byte + 3 address bytes + read/write data bytes

• ReadArray(LowFrequency): CMD = 0x03, ADH:ADM:ADL, MAX = 0x00..0xff
  • reads the requested number of bytes from the SPI FlashROM
  • start address is given by ADH:ADM:ADL (byte address!)

• ReadSectorProtection: CMD = 0x3c, ADH:ADM:ADL, MAX = 0x00
  • reads the sector protection status
  • 0x00 = sector unprotected
  • 0xff = sector protected

• PageProgram: CMD = 0x02, ADH:ADM:ADL, MAX = 0x00..0xff
  • programs up to 256bytes into FlashROM
  • start address should be a 256byte page (ADL == 0x00), otherwise data rollover can happen!
  • data to be written must be setup in the BlockRAM first
  • sector must be unprotected first
  • WriteEnable command must be issued first