Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.

First Address	Last Address	Implementation	Description
00	1F	internally writeable registers	common status registers (CommonStatusRegister)
20	3F	network writeable registers	common ctrl registers (CommonStatusRegister#CommonControlRegister)
40	48	ROM	board information ROM
50	5F	Times	board timers
60	7F		unused
80	BF	internally writeable registers	user defined status registers
C0	FF	network writeable registers	user defined control registers
0100	7FFF	TRBnet space	space reserved for TRBnet standardized functions
8000	FFFF	data / address port	forwarded to internal data port

Since it would cost to much resources to really implemented all the CTRL registers, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.

Protocol

All accesses with dtype 1111 are given to TrbNetAddresses. This is used for address allocation and readout of the unique ID.

A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.

Operation	dtype	F0	F1	F2	F3
single register read	1000	ADDR	unused
single register write	1001	ADDR	Data		CRC?
replying to register access	1000	ADDR	Data		CRC?

To provide a dma-like memory access to access and transfer bigger amounts of data for example from a fifo, the memory read / write operations are used. The protocol is similar to the one for single register access:

Operation	dtype	F0	F1	F2	F3	Comment
multiple read	1010	ADDR	Length		CRC?
multiple write	1011	ADDR	Config*		CRC?
		res.	Data		CRC?	repeated until all data is sent

When writing, the reply is generated from a single read to the last address. When reading, address and data is sent back. The length field gives 15bit number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty. The highest bit of the length field selects whether the address should be kept (0) or is continously counting up for each read (1).

Config(15) for the write access is the same as length(15) when reading: Enable signal for address counter.

The multiple access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request.

Access handling

TrbNetRegIO tries to handle all accesses to registers in a way which inhibits the "GTB effect". Accessing a non-existing register or an entitiy on the internal data bus which has deceased may under no circumstances lock up the slow control channel. Therefore the interface to the user register space must be bulletproof and completely decoupled from the slow control endpoint.

The TrbNetRegIO entity will handle an automatic timeout for accesses to the DAT_* bus. This timeout is a constant and the same for all TRBnet component. The value suggested here is 32 clock cycles yielding in 320ns, which is slow enough for slow control.

situation	read access	write access	notes
unknown address	DAT_UNKNOWN_ADDR_OUT	DAT_UNKNOWN_ADDR_OUT	ignore cycle, prepare for next access
entity is busy	DAT_NO_MORE_DATA_OUT	DAT_NO_MORE_DATA_OUT	temporary error, retry must be possible
everything OK	DAT_DATAREADY_OUT	DAT_WRITE_ACK_OUT	read data is OK, write data has been accepted
timeout	DAT_TIMEOUT_IN	DAT_TIMEOUT_IN	ignore cycle, prepare for next access

By this mechanism a broken entity on DAT_* bus can never lock up the slow control channel.

-- MichaelBoehmer - 15 Dec 2008

The SLAVE_BUS - an example for implementation

I have written a small example VHDL code which allows easy implementation of own (also more complex) registers / handlers on the DAT_* bus of TrbNetRegIO. It consists of a "bus handler" which converts the DAT_* signals to simple select, read and write strobes, and handles BUSY and ACK response from the slave entities. TIMEOUT and UNKNOWN_ADDR are also handled correctly. Besides, there's a generic register for setting control signals and reading back; this entity can also used as base for handlers of more complex tasks (like implementing a slow I2C master, as RICH needs it).

Just ask me for source code (Also available in the cvs, repository rich_adcm)

-- MichaelBoehmer - 16 Dec 2008

Ports & Generics

TrbNetRegIO connects to the network with a standard API-interface that is not shown here. The ports towards the application are as follows:

Port	Width	Description
STAT_RAM_WRITE_IN	1	write to the status ram
STAT_RAM_ADDRESS_IN	6	status ram address
STAT_RAM_DATA_IN	16	data to the status ram
STAT_RAM_DATA_OUT	16	data from the status ram
MY_ADDRESS_OUT	16	Trb_net_address of the endpoint
REGISTERS_IN	32*NUM_STAT_REGS	connection for status registers
REGISTERS_OUT	32*NUM_CTRL_REGS	connection for control registers
DAT_ADDR_OUT	16	internal address port
DAT_READ_ENABLE_OUT	1	internal read
DAT_WRITE_ENABLE_OUT	1	internal write
DAT_DATA_OUT	32	write data
DAT_DATA_IN	32	read data
DAT_DATAREADY_IN	1	read data is valid
DAT_WRITE_ACK_IN	1	write data has been accepted
DAT_NO_MORE_DATA_IN	1	finish transfer / no more data
DAT_UNKNOWN_ADDR_IN	1	unused address
DAT_TIMEOUT_OUT	1	endpoint timed out, access is canceled

Generic	Range	Description
NUM_STAT_REGS	0 - 6	Number of status registers is 2**NUM_STAT_REGS
NUM_CTRL_REGS	0 - 6	Number of control registers is 2**NUM_CTRL_REGS
INIT_CTRL_REGS	vector width: 2**NUM_CTRL_REGS*32	Init value for all control registers
USED_CTRL_REGS	vector width: NUM_CTRL_REGS	Which of the addressable register are used
USED_CTRL_BITMASK	vector width: 2**NUM_CTRL_REGS*32	which of the bits of the used registers are used
INIT_ADDRESS	16	Address, the endpoint should have on startup
INIT_UNIQUE_ID	63	The unique id on startup

Other Features

RegIO also serves as a base to several other applications like SPIFlashProgramming.

-- JanMichel - 13 Oct 2008