Readout Setup v1 : AddOnv1 and other outdated information

Rossendorf Dec07 discussion

In Rossendorf we had a discussion about the MDC readout project. The RossendorfDec07Minutes can be found here.

Task

We should connect 16 motherboards to the add_on card to read out one Mdc sector. Each transceiver (sn75976A) has 20 pins (9 channels). We have two transceivers for each motherboard and we want to read out 10 buses. So, the addon board receives as input signals about 180 data lines. It converts again the differential signal into TTL signals. The FPGA (VIRTEX from XILINX) receives Mdc information, process this data (LVL2 algorithm...) and sends this data to the TRB v2 through a 2 X 20 pins connectors (QTE-020-02-F-D-A).

Addon board design ideas

In this picture the transceiver used are (sn75976A).

What the Virtex in the addon board has to do:

-- AttilioTarantola - 27 Sep 2006

In this document a block diagram shows the main ideas to collect data from 16 motherboards as fast as possible.

Here the state machines I want to implement in my VHDL.

MDC-AddOn board documentation

Transceiver discussion

-- AttilioTarantola - 11 Aug 2006

Here a document in which I compare the main characteristic of the transceivers we are thinking to use. I compare transceivers from Texas Instrument, Analog Devices and Intersil.

MDC Add-Onv1: Data structure

-- AttilioTarantola - 28 Feb 2008

Here you find the structure of the data which is produced by the Add-On board. This data is transmitted to the TRB through the LVDS and TTL lines. The data bus is 26 bits width. In the first dataword I encode debug information: token back or not, bus number, event type (normal event or calibration event) and number of dataword in the event:

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
token status event type bus number (0..9) 0 0 0 0 Dataword number in the event

token status bit(25,24) 01 token is back to MDC Add-On.

token status bit(25,24) 10 token is NOT back to MDC Add-On. In this case the readout doesn't stop. It continuously runs with the error bit indicated.

The dataword structure which follow, will look like:

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Motherboard number(1..3) Bus number (0..15) TDC number (1..12) TDC Channel# 12-14:ch#(0..7), 11: hit#(0,1) Data

-- AttilioTarantola - 15 Mar 2008
  • few events: Data with the new data format. Calibration and TDC data sample. BUS 0 (or BUS A). Data coming from one short MB. I calibrate few channels per TDC.

How to start the MDC DAQ using Add-Onv1

-- AttilioTarantola - 15 Apr 2008

1. login in the ETRAX as ROOT.

2. program FPGA on TRB: ./TRBv2b_MDC.sh

3. set the environment: export DAQ_SETUP=pion9

4. program the FPGA on Add-On: /home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/plane_one/mdc_trb.stapl

5. enable calibration trigger: ./rw_mdc_addon w 0 0E 0

or disable calibration trigger: ./rw_mdc_addon w 0 0E 1

6. set the number of MBs which are connected to BUS 0:

(1 short MB): ./rw_mdc_addon w 0 7 1

(2 short MBs): ./rw_mdc_addon w 0 7 2

(1 long MB): ./rw_mdc_addon w 0 7 3

(2 long MBs): ./rw_mdc_addon w 0 7 4

7. reset: ./reset_fpga

8. begin run trigger: ./rwv2 w 0 6 80

9. start readout: ./readout_verbose -w 32000 -o UDP:192.168.0.1:30000

ROC and CAL configuration files

Configuration data for BUS0:

* MDC configuration data: MDC configuration data: BUS0

Howto change ROC/CAL parameters via Etrax

In the FPGA (Virtex) on the MDC Add-On the configuration data for BUS0 is stored in a RAM memory. If you want to change the configuration data, use the ./rw_mdc_addon program in "write mode" and set the device on number 5.

i.e. If on the BUS0, 1 long MB is connected and you want to set the threshold to 43, use the following commands:

./rw_mdc_addon w 5 17D 43

./rw_mdc_addon w 5 17F 43

./rw_mdc_addon w 5 181 43

./rw_mdc_addon w 5 183 43

./rw_mdc_addon w 5 185 43

./rw_mdc_addon w 5 187 43

If you want to verify the value you wrote use the rw_mdc_addon program in "read mode":

./rw_mdc_addon r 5 17D

./rw_mdc_addon r 5 17F

./rw_mdc_addon r 5 181

./rw_mdc_addon r 5 183

./rw_mdc_addon r 5 185

./rw_mdc_addon r 5 187

MDC Add-On and GP Add-On board display(SLR 2016)

- Cornelius Kleiner and Christian Kern - 22 Jul 2008

Event size in Au+Au collision at 1GeV for one MDC chamber:

Event size in Au + Au collision at 1GeV (J.Wustenfeld diplomarbeit)

20 particles for each chamber (6 layers), he supposes 20 channels fire

20(particles) X 6 (layers) X 2 (hits: l/t edges) = 240 datawords for all chains (16 motherboards) (here just estimation since it is possible that one particle let fire more than one TDC channel)

240(datawords) X 21 bits each = 5 Kbits

The FIFO (EVENT COLLECTOR),in the block diagram, has to take 5 Kbits, corresponding to the event of 20 particles firing.

Suppose LVL1: 10^5 reactions/sec (or one LVL1 each 10 μsec ) and between the LVL1 and the LVL2 there are 150 μsec, I have to be able to store 15 events in the FIFO(event collector) for example. Approximately its size should be: 15 (events) X 5 (Kbits each) = 75 Kbits.
  • Some "realisitic" estimation by C.Muentz: 7 wires per hit, add 10% noise -> equivalent to 8 wires per hit ("realistic estimate" from Ar+KCl). According to RQMD (M.Heilmann) the first plane is hit by 220 charged particels (central Au+Au at 1.5GeV) -> 37 hits per sector. Result: 37 x 8 x 2 = 568 datawords. This corresponds to 11.9 Kbits per event and chamber. Consequently, the FIFO size has to be (15 events stored): 180 Kbits.

I may suppose to transfer from my board to the TRB at this rate: 10^5 Hz x 5 Kbits = 500 Mbits/s
  • According to RQMD (M.Heilmann), central Au + Au at 1.5GeV:
PLANE I -> 220 charged particels -> 37 hits per sector -> 568 datawords -> 11.9 Kbits per event and chamber

PLANE II -> 190 charged particels -> as plane I

PLANE III -> -

PLANE IV -> 110 charged particels -> 18 hits per sector -> 288 datawords -> 5.5 Kbits per event and chamber

-- JanMichel - 26 Oct 2009
Topic attachments
I Attachment ActionSorted ascending Size Date Who Comment
MDC-setup.pdfpdf MDC-setup.pdf manage 279.6 K 10 Jul 2006 - 08:17 AttilioTarantola Michael's ideas for MDC readout
attilio_addonboard.pdfpdf attilio_addonboard.pdf manage 127.2 K 10 Jul 2006 - 08:14 AttilioTarantola my_addon board
block_diagramm_readout.pdfpdf block_diagramm_readout.pdf manage 18.5 K 04 Oct 2006 - 13:56 AttilioTarantola block diagramm
cal_and_norm_data.txttxt cal_and_norm_data.txt manage 6.0 K 15 Mar 2008 - 21:13 AttilioTarantola dataword sample
comparison_transceivers.pdfpdf comparison_transceivers.pdf manage 172.4 K 11 Aug 2006 - 10:12 AttilioTarantola tranceivers
config_virtex_ram.txttxt config_virtex_ram.txt manage 3.9 K 21 Apr 2008 - 09:23 AttilioTarantola MDC configuration data: BUS0
drawing_myboard.pdfpdf drawing_myboard.pdf manage 46.8 K 04 Oct 2006 - 13:41 AttilioTarantola layout
drawing_myboard_v2.pdfpdf drawing_myboard_v2.pdf manage 56.7 K 04 Oct 2006 - 13:42 AttilioTarantola layout_v2
my_state_machine_v2.pdfpdf my_state_machine_v2.pdf manage 53.4 K 27 Sep 2006 - 12:27 AttilioTarantola state machines
pin_myboard.pdfpdf pin_myboard.pdf manage 36.2 K 11 Aug 2006 - 10:19 AttilioTarantola QTE pins ideas
presentazione_myboard.pdfpdf presentazione_myboard.pdf manage 293.4 K 14 Jul 2006 - 07:58 AttilioTarantola more about the addon board..
Topic revision: r2 - 27 Oct 2009, JanMichel
 
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