Weekly meeting on MDC readout upgrade

Participants:

Kathrins report

• see pdf with measurements 1 to 8 boards.
• one noisy board (b) was found
• the other boards were all below 1 permille when adjusting the thresholds to about 50 (no individual tuning)
• looks good
• still needed is the CTS measurement
• report to Christian and decision!
• one new CTS cable at plane 3 sector 4 right side
• 1 MHz with function generator - some noise data were collected with varying threshold
• check with analog out for crosstalk/induced noise
• many CTS cables are produced (except for sector 1)
• measurements with simulated CTS were made see here

Jans report

• ethernet is not working on the hub (long packets)
• all OEP Voltages were measured by the internal ADCs
• look good with some exceptions were tuning/calibration of the ADC is required ( voltage divider).

Current measurements

• see first measurements here: MdcAddonCooperation
• proposal to make test with pulser firing all (or half of all) channels, then increase rate from 1 to 20 kHz (with reasonable thresholds)
• check rise of current (should stay below 1 A for long MBO)
• last OEP design leaves uninitialzed MBO at low current
• there are doubts that the threshold setting worked, has to be checked with proper init file script.

Voltage distribution board/ Fanpw2

• first board exists and is tested by Torsten
• changing return currents ( from 5V) influence ground for 3+-3V on daughterboards because they are unregulated on the OEP
  • solution 1: new OEP with regulation for +-3 V (problem: neg low power LDOs not available)
  • solution 2 (favoured): common ground cable: make test with massive copper ground cable
• Fanpw3 will be done ( 3 months )

latest tests in the cave

• with 8 OEPBs and daq was done successfully

Unpacker

• work has started including init from DB
• Joern will come to GSI mid July to work with Ilse and Attilio
• link to DataStructure
• link to OEPNetworkAddresses
• Michael will provide perl script for daq-anal, sniff, decode...
• see first tests
• done

Topics

• It works - but
• transfer too slow (FPGA to TRB?)
  • at GSI it runs with 75kHz
  • what's wrong at FZD?
  • no news yet
• edge triggered data reception in FPGA
  • double and triple hits on same address, 0-hits
  • on all MBOs?
  • only on chains of 2 or more MBOs?
• GDE signal derived from trigger, but MBO derived from CMS
  • GDE to late?
• GDE release during calibration
  • reset hit registers to early?
  • data ok?
• Make tests with pulser to measure electronics efficiency
• new tests with pulser LVL1 up to 1MHz
• high threshold with EB up to 20kHz - maybe the network with 10Mbits is the problem...
• shielding - not clear if efficient, new residual plots needed
  • see FZR results (added by CM)
  • my (CM) interpretation of the recent results: NO significant change of the noise level, i cannot recommend to install these additional shieldings, also due to the unclear influence of the HV current, reported by Jörn.
• charging up has to be investigated

decision on priority was taken

• priority
  • 1. switch fast to OEP
  • (fix all errors on current design)

current work at GSI

• Sector 4, layer 3 (POFs) and 4 started
• all cables and POFs should be fixed to chamber, not to supports
• new cable type for Common Stop needed (Michael)
• better labels needed (Kathrin)

OEP work

• Attilio reported about bit shifts in the FPGA
  • problem with Lattice design software
  • is manufacturer contacted? yes
  • problem not yet understood
  • comes and goes
  • now has disappeared
• one link is now working
  • with data and calibration triggers
  • short and long MBO working
  • data file with current data format needed
  • new data format (2 times in 1 32-bit word) not yet
• Jan is working on a 16 link version
  • ID info of several OEPs read out on hub
  • 8 links seem to work
  • problems with place and route software when more than 8 ports are used.
  • send problematic design to Lattice for help
  • still bit errors in media interface, sometimes dependend on recompilation of design, sometimes intermittent in time.
• patched TRB needed
• power distribution board to be tested (Kathrin) (5V, +-3V, 1.4V, 3.5V)
• power now supplied by Genesys power supplies
• test in cave with CMS needed for general green light
• LVDS CMS signal cabled up
• cross talk can be seen up to a distance of about 5mm
• watch out during cabling!!!
• needs now realistic cabling with more MBOs
• test in cave with 1 MBO and 1 OEPB was done, see pictures of noise TestsinCave
• qfile_009.tif: noise on analog readout during readout
• qfile_010.tif: noise on analog readout during readout
• qfile_011.tif: noise on analog readout during readout
• readout test was running whole night through
• agreement was reached on the possibility to switch between two different compression formats for debugging
• work starts now (SY) to get it in standard readout to HLD-files

New transmission problem 21. July

• Attilio reworked the FPGA code to support debugging
• sometimes empty events with some wordcount are sent
• problem seems to be in sending part
• has to be solved until next week
• solved

How to load thresholds and firmware

• manipulate threshold in Oracle, output to files
• automatic load via TRBnet to TDCs
• take threshold data from FPGA after update and insert into data stream?

efficiency measurements at FZD

• starts at 1900V (plateau), not understood yet, maybe gas mixture?
• try out Argon isobutan mix
• change gas flow (oxygen?)
• small gas leaks are fixed, but no significant improvement at 60/40 mix
• plateau at 1650 with 80/20 mix, see efficiency plateau
• new measurements with gas flow switched off indicate leakage and contamination (oxygen) when flow is too low
• He leak detection will be performed again
• O2 measurements at FZD, manual available now
• electrolyte cell was empty
• needs new evaluation