Common Status Register All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet....
Checklist of things to be checked before data taking in a beamtime Print this page and fill out gaps and give it to the technical coordinator Date: issue d...
DAQ Upgrade This document gives an overview of why and how we want to upgrade our HADES DAQ/Trigger System. The upgrade at a glance : ) . Motivation for an Upgr...
CTS and Trigger Logic addresses To all register when accessing vi trbnet add offset A0 CTS Address Bit range Meaning 91 15 downto 0 lvl1 trigger number...
Main.BurkhardKolb 14 Dec 2007 Agenda: 11.12.07 introduction Attilios Talk about MDC readout via TRB identified projects: TRB Add on board old driver cards ...
(NL) is a number of line counter tip_readout (DSP1) tipdebug sniff1 tof1tip (NL) CT:5 X:6100 MC:6407 MS:20040 1:1445d2 1T:0 1P: 3 2 :8b6c1 2 :b8f0e CT: which ...
In a nutshell: To remove tof completely from the LVL2 trigger and use tip only as a readout board, change * set g_master_control expr 0x6 $async_mode to...
IPU Data Channel Data Format The request to start readout of the data of a specific event is the same as the trigger information delivered on the LVL1 trigger ch...
Overview $ trbnet_full_endpoint.pdf : The hades_full_endpoint entity is the central part to connect to the network. Overview Short description of the ports ...
This text is stolen from Michael Bhmer: http://www hades.gsi.de/daq/rc99/richel_page.html A summary of the HADES trigger codes On this page you can find a summar...
LVL1 Trigger Definitions * All information about LVL1 triggers will be sent in a packet using TrbNet and the optical network. * A fast trigger strobe for ...