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Results from Main web retrieved at 23:05 (Local)

HadesDaqSlowControlGroup
HadesDaqSlowControlGroup Please change this topic to add new members in the HadesDaqSlowControlGroup: These are the members of HadesDaqSlowControlGroup: * Set ...
r108 - 2023-07-17 - 10:27 by BehruzKardan
HadesShowerGroup
Edit this topic to add a description to the HadesShowerGroup
r14 - 2016-09-18 - 23:00 by JerzyPietraszko
WikiUsers
List of Foswiki users Below is a list of users with accounts. If you want to edit topics or see protected areas of the site then you can get added to the list by ...
r1181 - 2024-04-26 - 11:53 by AdminUser
Number of topics: 3

Results from DaqSlowControl web retrieved at 23:05 (Local)

CrossTalk
Main.MarekPalka 16 Nov 2006 On the picture below is presented crosstalk measured on 2 channels. On one channel is pulse which is about 55ns wide. Disturbing chan...
r4 - 2006-11-20 - 09:46 by MarekPalka
CypressPart
Main.MarekPalka 29 May 2006 Cypress registers
NEW - 2006-05-29 - 14:10 by MarekPalka
DescriptionOfFPGA
A VIRTEX4 LX40 FPGA is used on the TRBv2. FPGA registers r/w adress bits r 0 31 26 not used ADO_LV 25 0 r 1 31 lvl2 busy 30:lvl1_fif...
r8 - 2008-07-23 - 17:14 by MarekPalka
DescriptionOfTDC
TDC is connected with FPGA thru two interfaces: * JTAG * Parallel JTAG interface It is used for programming status register and control register of TDC's...
r3 - 2007-07-24 - 15:43 by MarekPalka
JamProgramming
Main.MarekPalka 29 May 2006 How to programm Cypress jam p0xb5200000 aCONFIGURE_DEVICE cy_top.stp Programm board with base 0xb. rw w 0xb5200004 90 for Cypress ...
NEW - 2006-05-29 - 14:09 by MarekPalka
MatchingUnitV2
Main.MarekPalka 29 May 2006 * XilinxPart * CypressPart * JamProgramming
NEW - 2006-05-29 - 13:49 by MarekPalka
NewCTS
CTS and Trigger Logic addresses To all register when accessing vi trbnet add offset A0 CTS Address Bit range Meaning 91 15 downto 0 lvl1 trigger number...
r24 - 2010-05-18 - 12:59 by MarekPalka
NewProtocolEtraxToFPGA
Main.MarekPalka 02 Nov 2006 Port C7 0 is used as an output of Etrax and port C15 8 is used as input. With first trigger etrax sends what kind of action(M) i...
r7 - 2007-02-09 - 14:29 by MarekPalka
SpeedImprovement
Current speed: 1000 Event/sec goal: 5000 Event/sec check waitstates waitstates application: Results: * speed the application with empty loop (it ...
r5 - 2006-09-22 - 13:44 by RadekTrebacz
TDCReadoutBoardV2Beam2012
When restart of the DAQ and reprogramming of the FPGAs does not help First try to login to etraxpXXX Check if the home directory (ls /home/hadaq/) on the Etrax is...
r3 - 2012-03-26 - 11:46 by MarekPalka
TDCprogrammingViaJam
How to generate jam and tcl files In view of growing number of TRBs the make.pl perl script was made to produce jam files with TDC settings and channels enabled/d...
r15 - 2010-01-01 - 16:04 by JanMichel
TRBBoardStatus
Here the TRB Version 1 are listed where they are used and their current status de etrax where status additional information last update 001 cracow Ok ...
r16 - 2007-03-14 - 09:31 by MarekPalka
TRBvIIHowTo
How to use the TRBv2 * How to start * How to start readout * DescriptionOfEtrax * DescriptionOfFPGA * DescriptionOfTDC Main.MarekPalka 27 Jun 2...
r8 - 2008-01-07 - 10:40 by RadekTrebacz
WebNotify
This is a subscription service to be automatically notified by e mail when topics change in this DaqSlowControl web. This is a convenient service, so you do not h...
r12 - 2015-07-06 - 14:34 by BurkhardKolb
WebStatistics
Statistics for DaqSlowControl Web Month: Topic views: Topic saves: File uploads: Most popular topic views: Top contributors for topic save and up...
r423 - 2024-04-28 - 00:00 by AdminUser
XilinxPart
Main.MarekPalka 29 May 2006 Xilinx registers Address 0x0: bits 7 6 5 4 3 2 1 0 TDO of jtag port CY_config_done pin status ...
NEW - 2006-05-29 - 14:00 by MarekPalka
Number of topics: 16
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