Level 1 trigger processing by VULOM3 board

The old triggerbox has now been replaced by an FPGA module and can be remotely controlled by EPICS. Here is provided some documentation for both debug and normal operation.

• report.pdf: Provides an overview about the functionality of the board.

• logic_diagram.pdf: Shows the interconnection between all different function blocks inside the FPGA.

• Pinout_and_mux_values.pdf: Contains front panel pinout and a key to multiplexer numeric values.

• Vmeaddress.pdf: Lists VME addresses for every given register. It can be used with the "rw" command for debug or when the EPICS interface is not available. (VMEAddressesForEveryGivenRegister)

• Vulom3_schematic.pdf: Contains the electrical schematic.

Some comments about the TRB bus:

• The data transmission to TRB consists of 2 data lines and one clock line running at 50 MHz. Data must be read on the rising edge.
• The packet pattern is the following:
  • "01", "10", "01", "10" synchronization sequence;
  • Normal ("01") or calibration ("11") code;
  • 16 bit tag;
  • 16 bit latches information (msbyte accepted, lsbyte received);
  • 32x8 bit scalers (PT1, PT2, PT3, PT4, PT5, TS, VS, dead);
  • 32 bit checksum, sum of data transmitted after the synchronization sequence
• After the packet transmission the triggerbox waits for a 100 ns (or more) pulse given by TRB on the acknowledge line, then goes to the idle state. Otherwise, if TRB sends a 100 ns (or more) retx pulse, the same packet is retransmitted.

DavideLeoni - 29 Feb 2008