Level 1 trigger processing by VULOM3 board

The old triggerbox has now been replaced by an FPGA module and can be remotely controlled by EPICS. Here is provided some documentation for both debug and normal operation.

  • report.pdf: Provides an overview about the functionality of the board.

  • logic_diagram.pdf: Shows the interconnection between all different function blocks inside the FPGA.

Some comments about the TRB bus:
  • The data transmission to TRB consists of 2 data lines and one clock line running at 50 MHz. Data must be read on the rising edge.
  • The packet pattern is the following:
    • "01", "10", "01", "10" synchronization sequence;
    • Normal ("01") or calibration ("11") code;
    • 16 bit tag;
    • 16 bit latches information (msbyte accepted, lsbyte received);
    • 32x8 bit scalers (PT1, PT2, PT3, PT4, PT5, TS, VS, dead);
    • 32 bit checksum, sum of data transmitted after the synchronization sequence
  • After the packet transmission the triggerbox waits for a 100 ns (or more) pulse given by TRB on the acknowledge line, then goes to the idle state. Otherwise, if TRB sends a 100 ns (or more) retx pulse, the same packet is retransmitted.

DavideLeoni - 29 Feb 2008
Topic attachments
I Attachment Action Size Date Who Comment
Pinout_and_mux_values.pdfpdf Pinout_and_mux_values.pdf manage 3.1 K 13 Sep 2008 - 15:42 MarekPalka Board pinout and multiplexer values
Pinout_and_mux_values.txttxt Pinout_and_mux_values.txt manage 2.7 K 13 Sep 2008 - 15:37 MarekPalka Board pinout and multiplexer values
Vmeaddress.pdfpdf Vmeaddress.pdf manage 2.7 K 12 Sep 2008 - 12:44 MarekPalka Vme addresses
Vulom3_schematic.pdfpdf Vulom3_schematic.pdf manage 410.6 K 10 Oct 2007 - 15:43 DavideLeoni Vulom 3 schematic
logic_diagram.pdfpdf logic_diagram.pdf manage 45.0 K 29 Feb 2008 - 22:18 DavideLeoni Logic diagram
report.pdfpdf report.pdf manage 42.5 K 29 Feb 2008 - 22:41 DavideLeoni GSI Report
Topic revision: r11 - 12 Dec 2009, JanMichel
 
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