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You are here: Foswiki>DaqSlowControl Web>WebChanges (2001-08-16, PeterThoeny)Edit Attach
50 recent changes in DaqSlowControl Web retrieved at 11:23 (Local)
TDCReadoutBoardV2cErrors
Add connection between temperature sensor and FPGA (additional to connection to Etrax) (Fix on Trbv2: wire from via next to Pin1 of temperature sensor to JP266 te...
r3 - 2009-10-27 - 11:48 by JanMichel
TDCReadoutBoardV2bErrors
* The add on connector should be: QTE 040 02 (larger distance between TRB and add on, no impact for the user! Main.MichaelTraxler 05 Jun 2007
r2 - 2009-10-27 - 11:48 by JanMichel
TRBBoardErrors
Errors found in previous design versions * Things we learned from ETRAX_FS_DEV1 * Errors in TRBv2A * Errors in TRBv2B * Errors in TRBv2C * Errors f...
NEW - 2009-10-27 - 11:48 by JanMichel
TDCReadoutBoardV2Errors
LIST OF ERRORS FOUND IN THE TRBv2A DESIGN: * Event and bunch reset signals for TDCs come from FPGA to all four TDCs. In V2 those signals are LVDS and FPGA sho...
r9 - 2009-10-27 - 11:47 by JanMichel
TRBTigerSHARC
TigerSHARC PIN Number of CMOS PINs Comments PINs connected to Virtex4 SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0 SCLK 1...
r2 - 2009-10-27 - 11:45 by JanMichel
OEPBasicTests
Initialize new OEPs I. Connect JTAG cable, then power cable I. Check that 1 LED is on I. Program board via JTAG from IspVM. * Program FPGA directly...
r4 - 2009-10-26 - 15:31 by JanMichel
InformationForOEPMounting
Mounting new Cables and OEP to MDC In this file you can find all information you need before working on the MDC upgrade: * MboDboOnChamber.pdf: INFORMATION FOR...
r11 - 2009-10-26 - 15:31 by JanMichel
SecondRadiationTest
Main.AttilioTarantola 26 Aug 2008 The Optical end point placed at the end of the HADES cave. The logical analyzer connected to hades29. D0: external oscillator D1...
r2 - 2009-10-26 - 15:26 by JanMichel
RossendorfDec07Minutes
Main.BurkhardKolb 14 Dec 2007 Agenda: 11.12.07 introduction Attilios Talk about MDC readout via TRB identified projects: TRB Add on board old driver cards ...
r5 - 2009-10-26 - 15:19 by JanMichel
MdcDcLvl2
Main.AttilioTarantola 25 Mar 2009 MDC DC LVL2 status Board Number where are used status additional information last update 001 Frankfurt Uni Ok ...
r3 - 2009-10-26 - 15:17 by JanMichel
MdcDcLvl1
Main.AttilioTarantola 13 Feb 2009 MDC DC LVL1 status Board Number where are used status additional information last update 001 GSI M.T.Lab Ok ...
r3 - 2009-10-26 - 15:16 by JanMichel
HowToRunMDCDaq
Main.AttilioTarantola 05 Aug 2008 The software configures and takes data from 10 buses. By default all 10 buses are enabled. After you loaded the firmware, the ch...
r18 - 2009-10-26 - 15:12 by JanMichel
TRBSchematicsCollection
Schematics collection * can be found here: DaqSlowControl.TDCReadoutBoardV2#Schematics_Pinout_and_Patches_of Main.MichaelTraxler 17 Dec 2007
r2 - 2009-10-26 - 13:56 by JanMichel
CommonStatusRegister
Common Status Register All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet....
r18 - 2009-10-19 - 18:16 by MichaelBoehmer
TrbNetDatafields
Common definitions for the use of TRBNets datafields Packet types The packet type is sent with each 64 bit packet Name Type Description F1 F2 F3 ...
r23 - 2009-10-08 - 13:50 by JanMichel
SPIFlashProgramming
SPI controller description The SPI FlashROM controller is attached to RegIO data bus. The user interface consists of two 32bit registers, and one BlockRAM for dat...
NEW - 2009-09-11 - 12:57 by JanMichel
TrbNetRegIO
Reading and Writing registers over the network TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network....
r18 - 2009-09-11 - 12:24 by JanMichel
MdcReadoutupgrademeeting
Weekly meeting on MDC readout upgrade Main.BurkhardKolb 08 Sep 2009 Participants: Main.BurkhardKolb, Main.JanMichel, Main.JoernWuestenfeld, Main.KathrinGoeb...
r45 - 2009-09-08 - 13:22 by BurkhardKolb
TrbNetStreamedEventBuilding
Streamed Event Building The name "streamed event building" comes from the fact that inside the network there is no place where we can guarantee to be able to stor...
r9 - 2009-07-09 - 12:49 by JanMichel
AddOns
Main.MichaelTraxler 24 Jun 2009
NEW - 2009-06-24 - 16:56 by MichaelTraxler
TestsinCave
Tests in the Cave Test with internal CMS * yellow: CMS * purple: Token In * green: Token Out * red: Analog Out Main.KathrinGoebel 19 Jun 2009
r2 - 2009-06-19 - 17:30 by KathrinGoebel
TrbNetIPUChannel
IPU Data Channel Data Format The request to start readout of the data of a specific event is the same as the trigger information delivered on the LVL1 trigger ch...
r4 - 2009-05-28 - 15:18 by JanMichel
HowtoAddNewModule
In the base dir, change the files Makefile.am and configure.in make the new subdir and copy a Makefile.am from a different subdir (not from the main dir!!!). Edit...
r3 - 2009-03-25 - 15:42 by SergeyYurevich
VHDLConstraints
Information on using VHDL Constraints Lattice constraints Constraints for Lattice FPGAs should be located in a separate LPF file, especially if these constraints...
r7 - 2009-02-17 - 12:44 by MichaelBoehmer
HPTDCcalibration
Main.KrzysztofKorcyl 19 Sep 2005 RPC board CALIBRATION Calibration, according to NASA definition, is the process of collecting instrument characterization infor...
NEW - 2009-01-28 - 16:53 by MichaelTraxler
RichFEEandDAQUpgrade
First light : ) Despite the fact the the description below is really outdated, I can pronounce the first really important step from connecting the new RICH ADCM t...
r3 - 2008-12-22 - 17:51 by MichaelBoehmer
NewTriggerBusToDo
Not the official milestones, but some pragmatic steps: Simulations VHDL simulation done by Ingo. First important step is to have a running chain with 2 dummy APL...
r8 - 2008-12-22 - 13:29 by JanMichel
ModuleReleases
Stable releases of modules, corresponding CVS tags and description of each release are given in a table below: (How to checkout branch: cvs checkout r stab_oct07...
r2 - 2008-12-11 - 17:57 by SergeyYurevich
TrbNetAddresses
Network Addresses Each network member needs an unique 16Bit address. A network member is not necessarily equal to some piece of hardware: A normal TRB2 board has ...
r9 - 2008-10-28 - 12:02 by JanMichel
DescriptionOfEtrax
spi for Tof This site is still waiting for Marek :)
r5 - 2008-10-24 - 10:42 by RadekTrebacz
HadesRawDataFormat
HADES raw data format document is signed up to version 1.3 Purpose This document describes the raw data format of the HADES data acquisition system. All Rea...
r8 - 2008-10-02 - 12:01 by MichaelBoehmer
DaqUpgradeSubEventAdvancedDebugBlock
Main goal The Advanced Subevent Debug Block (ASDB) is being proposed in strict accordance to the existing HADES subevent header structure. It enhances the feature...
r2 - 2008-10-02 - 12:00 by MichaelBoehmer
DaqUpgradeSubEventDebugBlock
Structure The main idea is to include additional debug information inside the data block (either send by TRBNet or on the classical way). This information should ...
r4 - 2008-08-21 - 21:10 by MichaelTraxler
DescriptionOfFPGA
A VIRTEX4 LX40 FPGA is used on the TRBv2. FPGA registers r/w adress bits r 0 31 26 not used ADO_LV 25 0 r 1 31 lvl2 busy 30:lvl1_fif...
r8 - 2008-07-23 - 17:14 by MarekPalka
VMEAddressesForEveryGivenRegister
VME addresses for every given register This is the official source of information. Address Description comments offset (hex) ...
r2 - 2008-06-25 - 17:32 by MichaelTraxler
MDC-Optical_endpoint_History
I propose to use the following components: * SPFEIM100_G optical transceiver from Infineon (I ordered 30 of them 2007 01 29 ) * a 100 300Mbits/s SERDES. In...
r6 - 2008-06-06 - 21:05 by AttilioTarantola
TrbNetOnewire
Trb Net Onewire interface This entity provides a very simple 1 wire master to read out the id of a 1 wire device. It does not support busses with more than one de...
r2 - 2008-04-03 - 17:41 by JanMichel
TrbNetIOBUF
Overview The TrbNetIOBUF is the basic element which controls the connection between the media layer (after de multiplexing of the individual channels) and the Fan...
r12 - 2008-03-25 - 13:19 by JanMichel
TrbNetFifo
Overview Wrapper entity for various fifos. The design files for the different fpgas can also be found in the cvs, as xco configuration files for the xilinx corege...
r4 - 2008-03-14 - 23:42 by JanMichel
TrbNetStreamingAPI
Trbnet Streaming API A streaming API allows an application to be inserted into the data stream. There it can fullfill two different tasks: It can simply preproces...
r3 - 2008-03-14 - 23:09 by JanMichel
TRBProgressReports
Radek TIPS about DAQ, kernel, etc. manual about DAQ readout scripts TRBvIIHowTo for trb v2 AnaSimMay07 1 Quantum Mechanic very well ...
r87 - 2008-03-11 - 10:35 by AttilioTarantola
CN2008_02_Pictures
Main.MichaelTraxler 06 Mar 2008 * Front side: * Back side:
NEW - 2008-03-06 - 21:42 by MichaelTraxler
ModulReleases
Stable releases of modules, corresponding CVS tags and description of each release are given in a table below: Module CVS tag comment hadaq ...
NEW - 2008-02-22 - 12:32 by SergeyYurevich
EventBuilderPermormance01
Event Builder Performance Conditions: * 90 subsystems * I used TOF 0, TOF 1, TOF 2 and TOF 4 VME CPUs. 23/22 daq_rdosoft processes per CPU. * Water mark ...
NEW - 2008-02-08 - 19:21 by SergeyYurevich
TrbNetConfiguration
Network configuration A lot of parameters cn be set using the generics in each top entity. Nevertheless, some of these have to be common for all network devices. ...
r3 - 2008-01-22 - 15:17 by JanMichel
TRBvIIHowTo
How to use the TRBv2 * How to start * How to start readout * DescriptionOfEtrax * DescriptionOfFPGA * DescriptionOfTDC Main.MarekPalka 27 Jun 2...
r8 - 2008-01-07 - 10:40 by RadekTrebacz
NewTriggerBusNetwork
Overview The network protocol is the most critical part of the complete concept. It should match the requirements (low latency), but should be flexible on the o...
r19 - 2007-12-28 - 17:38 by JanMichel
NewTriggerBusCom
Please make a block diagram Please add schematics here... Bugs The trigger bus jumpers are not correctly pulled: To be a DTU, the data pin must be a pull up, not...
r5 - 2007-12-28 - 17:32 by JanMichel
TrbNetEndpoints
Endpoints There are some ready to use endpoints. These endpoints are named accordingly to their kind and number of interfaces: For example "trb_net16_endpoint_0_t...
NEW - 2007-12-28 - 17:04 by JanMichel
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