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You are here: Foswiki>DaqSlowControl Web>WebChanges (2001-08-16, PeterThoeny)Edit Attach
50 recent changes in DaqSlowControl Web retrieved at 00:43 (Local)
TrbNetInterfaces
Interfaces The TRB Endpoints are all using the same interfaces. There is a media independent interface (MII) on the network side. On the application side of the e...
r2 - 2007-12-28 - 16:33 by JanMichel
TrbNetIOMultiplexer
Overview The multiplexer, which has more than one port on the internal side, and one port only on the media side. Signal description Media direction port Inter...
r3 - 2007-12-28 - 16:15 by JanMichel
TrbNetOBUF
Overview The TrbNetOBUF is controlling what data content is leaving the hub. Signal description Media direction port (similar as described in NewTriggerBusMedia...
r3 - 2007-11-27 - 13:18 by JanMichel
TrbNetIBUF
Overview The TrbNetIBUF is buffering the data coming from the media. All word which are offered by the media must be read, otherwise something is completly wrong ...
r6 - 2007-11-27 - 13:17 by JanMichel
TrbNetFiles
TRBNet Files This is a list of files found in the cvs. The optical link is missing at the moment. Low level parts Fifos $ trb_net_fifo: A standard fifo entit...
r5 - 2007-11-27 - 12:34 by JanMichel
GeneralDescription
How to start 1. Below you can find images for TRB. If you cannot find your image, mail to Radek(rtrebacz #64;gmail.com). Lets include information about NFS ser...
r11 - 2007-11-27 - 10:26 by RadekTrebacz
LinuxVMECPUInstallation
The Concurrent VP32x/02x VME CPUs boot via PXE. To get this working you have to enable booting via PXE in the BIOS of the CPU. Additionally, one should enable the...
r8 - 2007-08-15 - 16:13 by MichaelTraxler
RpcDataStructure
TRBv1 structure Word: Contents: Description: # RPC Header 1 size Length of whole subevent 2 0x3001 ...
r11 - 2007-08-01 - 11:29 by MichaelTraxler
DescriptionOfTDC
TDC is connected with FPGA thru two interfaces: * JTAG * Parallel JTAG interface It is used for programming status register and control register of TDC's...
r3 - 2007-07-24 - 15:43 by MarekPalka
VHDLCodeInformation
General Information about VHDL Code 1 Recommendations for a common VHDL code style 1 Using VHDL Constraints Main.JanMichel 03 Jul 2007
NEW - 2007-07-03 - 13:45 by JanMichel
MarekPalka
Main.MarekPalka 02 Mar 2007 MarekPalka Main tasks are: * Crosstalk(CrossTalk) and nonlinearity TDC calibration started , * Implement internal registers ...
r5 - 2007-06-27 - 17:56 by MarekPalka
SoftwareHowToDataAccessBeamtimeAprMay2006
connect_res start/stop connect_res Michael fixed connect_res which was crashing when a connection to the Event Server (hadeb06) was lost. Now connect_res will...
r6 - 2007-04-22 - 19:13 by SergeyYurevich
DataAccessSchemeBeamtimeAprMay07
Data Access Scheme for Beamtime Apr 2007 The following picture illustrates the data flow for the april 2007 beamtime. This scheme on one hand provides access for...
r11 - 2007-04-12 - 15:16 by SergeyYurevich
TofParams
In a nutshell: To remove tof completely from the LVL2 trigger and use tip only as a readout board, change * set g_master_control expr 0x6 $async_mode to...
r4 - 2007-03-29 - 15:51 by IngoFroehlich
RunControlSoundServer
The sound server is a "superdaemon" running on "hadesdaq", as well as on hadc08 and lxhadesdaq Install the sound server: * checkout the "tools" module * as ...
r3 - 2007-03-26 - 15:56 by IngoFroehlich
ViewLogic
Graphical design system for logic designs. Main.MichaelBoehmer 20 Mar 2007
NEW - 2007-03-20 - 14:53 by MichaelBoehmer
TRBBoardStatus
Here the TRB Version 1 are listed where they are used and their current status de etrax where status additional information last update 001 cracow Ok ...
r16 - 2007-03-14 - 09:31 by MarekPalka
TrbNetPriorityArbiter
Overview The TrbNetPriorityArbiter takes an INPUT_IN pattern and generate an RESULT_OUT pattern with only one bit enabled. Fixed priority is possible as well as r...
NEW - 2007-02-14 - 13:54 by IngoFroehlich
NewProtocolEtraxToFPGA
Main.MarekPalka 02 Nov 2006 Port C7 0 is used as an output of Etrax and port C15 8 is used as input. With first trigger etrax sends what kind of action(M) i...
r7 - 2007-02-09 - 14:29 by MarekPalka
NewProtocolEtraxToDSP
The access to the DSP goes always via the FPGA, in particular the boot strap pins are driven by the FPGA, and this is very important. I suggest a number of regist...
NEW - 2007-01-29 - 12:09 by IngoFroehlich
NewTriggerBusNetworkDescr
HDR F1 Source address F2 Target address F3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LAY VERS SEQNR DTYPE ...
r3 - 2006-12-08 - 16:47 by IngoFroehlich
CrossTalk
Main.MarekPalka 16 Nov 2006 On the picture below is presented crosstalk measured on 2 channels. On one channel is pulse which is about 55ns wide. Disturbing chan...
r4 - 2006-11-20 - 09:46 by MarekPalka
MatchingUnitCode
Here is the code (in the attachment): matching.c and trigger.c are the most interesting files I think.... Main.MichaelTraxler 16 Jun 2005
r3 - 2006-10-12 - 17:21 by MichaelTraxler
SpeedImprovement
Current speed: 1000 Event/sec goal: 5000 Event/sec check waitstates waitstates application: Results: * speed the application with empty loop (it ...
r5 - 2006-09-22 - 13:44 by RadekTrebacz
AcromagModule
Driver installation for the Acromag PMC module * Download the driver software from acromag (or ask Ingo) * Go to pmcdx501/devdx501/ and #define KERNEL_DBG_O...
r2 - 2006-08-17 - 14:00 by IngoFroehlich
LvmeForConcurrent
Porting the LVME library to Concurrent VME CPU Notes Modules in Test Crate $ SAM: 0x33300000 $ CAEN: 0xeeee0000 $ DTU: 0x44000000 ToDo * Remove D8...
r3 - 2006-08-17 - 13:55 by IngoFroehlich
EtraxEPICSHowTo
Changes needed to compile EPICS environment: set environment: . init_env go to the directory: cd ~/devboard work_2.4/apps/epics/base 3.14.8.2 edit ./configure...
r9 - 2006-07-21 - 11:39 by MichaelTraxler
TRBUseDocumentation
Main.MichaelTraxler 22 Nov 2005 CPLD on board configuration The usage of CPLD is involved with SWITCH2 and also with register in FPGA. Vi this CPLD we can progra...
r2 - 2006-07-14 - 15:24 by MarekPalka
CypressPart
Main.MarekPalka 29 May 2006 Cypress registers
NEW - 2006-05-29 - 14:10 by MarekPalka
JamProgramming
Main.MarekPalka 29 May 2006 How to programm Cypress jam p0xb5200000 aCONFIGURE_DEVICE cy_top.stp Programm board with base 0xb. rw w 0xb5200004 90 for Cypress ...
NEW - 2006-05-29 - 14:09 by MarekPalka
XilinxPart
Main.MarekPalka 29 May 2006 Xilinx registers Address 0x0: bits 7 6 5 4 3 2 1 0 TDO of jtag port CY_config_done pin status ...
NEW - 2006-05-29 - 14:00 by MarekPalka
MatchingUnitV2
Main.MarekPalka 29 May 2006 * XilinxPart * CypressPart * JamProgramming
NEW - 2006-05-29 - 13:49 by MarekPalka
MatchingUnitExperts
## README ## $Source: /var/www/hades wiki.gsi.de/data/DaqSlowControl/MatchingUnitExperts.txt,v $ ## $Id: MatchingUnitExperts.txt,v 1.6 2006/04/21 08:45:52 HadesDa...
r6 - 2006-04-21 - 10:45 by HadesDaq
RichCratesRcPrcSetup
Main.MichaelTraxler 02 Feb 2006 * Overview of RICH:
NEW - 2006-02-02 - 19:04 by MichaelTraxler
VMEHandbookScan
VME info Main.MichaelTraxler 27 Jan 2006 * VME_Handbook_Pindefinition.pdf: Pins on the VME backplane * VME_Handbook_Interrupts.pdf: Interrupts * VME_...
NEW - 2006-01-27 - 12:18 by MichaelTraxler
MatchingUnitDataFormat
/* Version: $Source: /var/www/hades wiki.gsi.de/data/DaqSlowControl/MatchingUnitDataFormat.txt,v $ $Id: MatchingUnitDataFormat.txt,v 1.7 2006/01/23 13:28:19 Micha...
r7 - 2006-01-23 - 14:28 by MichaelTraxler
MatchingUnitAlgorithm
What the MU does in words.... One comment about downscaling and triggered flag in the MU data These flags are not correlated. The MU always (for every event) det...
r6 - 2006-01-18 - 16:31 by MartinJurkovic
SmokedTRB
The smoked TRB (Serial No. 5) is in repair. After removing the DC/DC converters (48V, 2,5V, 3.0V) there is no short circuit anymore and the ETRAX is working again...
r3 - 2005-11-09 - 12:12 by MichaelTraxler
TofCalibration
The TIP has to provide theta and phi of lepton candidates for the Matching Unit. Therefore it needes the calibration parameters of the TOF detector. There is no a...
r2 - 2005-09-16 - 22:27 by HadesDaq
RichHitsObservation
To observe the hits on the Rich detector one has to type: 1 ssh hrich@lxi003 1 bash ; daq_sniff h lxhadesdaq richmonqt Main.MichaelTraxler 14 Sep ...
NEW - 2005-09-14 - 20:06 by MichaelTraxler
CaenTDC32
CAEN TDC/ADC 32 channels Current (15.04.2005) firmware version 4.06 Way to find out version: E7_25:tof1:/hades/usr/hades/aug04/slow $ rw_16 r 50001000 read: 000...
r2 - 2005-08-25 - 17:25 by SimonLang
NEW - 2005-08-25 - 15:47 by SimonLang
TofSetup
This is the page where all TOF modules are described If you make changes (in particular TOF4) please update this page TIP modules Module Label Description ...
r11 - 2005-08-08 - 12:27 by IngoFroehlich
TofBugs
TIP shows permanent bus errors If the error log shows messages like this: e7_21 tipctrl 26 : tof2tip: Bus Error Workaround: Please stop DAQ, close hadaq and re...
r3 - 2005-08-05 - 11:46 by HadesDaq
TofDebugging
(NL) is a number of line counter tip_readout (DSP1) tipdebug sniff1 tof1tip (NL) CT:5 X:6100 MC:6407 MS:20040 1:1445d2 1T:0 1P: 3 2 :8b6c1 2 :b8f0e CT: which ...
r2 - 2005-08-05 - 11:45 by HadesDaq
TipSubeventFormat
TDC header (defined by CAEN) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...
r6 - 2005-08-05 - 11:43 by HadesDaq
RamEthernet
There are two applications: ram2eth file:///misc/hadaq/cvsroot/rpctrbetrax/eth2file response for sending triggers reading RAM1, RAM2 sending this data v...
r7 - 2005-07-14 - 14:19 by RadekTrebacz
RichAdjustThresholds
Adjust Thresholds cat s3r0p6.dat perl ne 'next if (/^#/); ($a, $b)=$_=~/(\d ) (\d )/; if($b s3r0p6.dat_all_1023 postion: sep03/slow/race/adjust_thresholds_fil...
r2 - 2005-07-13 - 15:18 by MichaelTraxler
MotherboardDACs
On the RPC Motherboard, there are 8 DACs from Linear Technologies: LTC2600 Manual is attached. Main.MichaelTraxler 13 Jul 2005
NEW - 2005-07-13 - 11:58 by MichaelTraxler
RunControlTasks
Status and "to do" list for RunControl * error reporting in async record? report via alarm status, how to check? * snc compiler works, but no runtime If cas...
r18 - 2005-06-02 - 14:38 by SimonLang
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Topic revision: r1 - 2001-08-16, PeterThoeny
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